Method and apparatus for normalizing thermal gradients over semiconductor chip designs

ABSTRACT

A method and apparatus for normalizing thermal gradients over semiconductor chip designs is provided. One embodiment of a novel method for normalizing an expected thermal gradient includes determining a location of the thermal gradient in the semiconductor chip design and inserting at least one supplemental heat source into the semiconductor chip design such that the thermal gradient is normalized by heat dissipated by the supplemental heat source.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.11/215,783, filed Aug. 29, 2005, which is a continuation-in-part of U.S.patent application Ser. No. 10/979,957, field Nov. 3, 2004. In addition,application Ser. No. 11/215,783 claims the benefit of U.S. ProvisionalPatent Application No. 60/605,889, filed Aug. 30, 2004.

FIELD OF THE INVENTION

The present invention generally relates to semiconductor chip design,and more particularly relates to the thermal analysis of semiconductorchip designs.

BACKGROUND OF THE INVENTION

Semiconductor chips typically comprise the bulk of the components in anelectronic system. These semiconductor chips are also often the hottestpart of the electronic system, and failure of the system can often betraced back to thermal overload on the chips. As such, thermalmanagement is a critical parameter of semiconductor chip design.

FIG. 1 is a schematic diagram illustrating an exemplary semiconductorchip 100. As illustrated, the semiconductor chip 100 comprises one ormore semiconductor devices 102 a-102 n (hereinafter collectivelyreferred to as “semiconductor devices 102”), such as transistors,resistors, capacitors, diodes and the like deposited upon a substrate104 and coupled via a plurality of wires or interconnects 106 a-106 n(hereinafter collectively referred to as “interconnects 106”). Thesesemiconductor devices 102 and interconnects 106 share power, therebycausing a distribution of temperature values over the chip 100 that mayrange from 100 to 180 degrees Celsius in various regions of the chip100.

In addition to large absolute temperatures, large variations in thethermal gradient over a semiconductor chip can cause the chip to fail inoperation. Thus, accurate knowledge of the expected thermal gradient iscritical in determining the layout of the chip. Unfortunately, thoughmany methods exist for performing thermal analysis of semiconductorchips, such conventional methods typically fail to provide a complete oran entirely accurate picture of the chip's operating thermal gradient.For example, typical thermal analysis models attempt to solve thetemperature on the chip substrate, but do not solve the temperature in afull three dimensions, e.g., using industry standards design, packageand heat sink data. Moreover, most typical methods do not account forthe sharing of power among semiconductor devices and interconnects,which distributes the heat field within the chip, as discussed above.

Therefore, there is a need in the art for a method and apparatus fornormalizing thermal gradients over semiconductor chip designs.

SUMMARY OF THE INVENTION

A method and apparatus for normalizing thermal gradients oversemiconductor chip designs is provided. One embodiment of a novel methodfor normalizing an expected thermal gradient includes determining alocation of the thermal gradient in the semiconductor chip design andinserting at least one supplemental heat source into the semiconductorchip design such that the thermal gradient is normalized by heatdissipated by the supplemental heat source.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited embodiments of theinvention are attained and can be understood in detail, a moreparticular description of the invention, briefly summarized above, maybe had by reference to the embodiments thereof which are illustrated inthe appended drawings. It is to be noted, however, that the appendeddrawings illustrate only typical embodiments of this invention and aretherefore not to be considered limiting of its scope, for the inventionmay admit to other equally effective embodiments.

FIG. 1 is a schematic diagram illustrating an exemplary semiconductorchip;

FIG. 2 is a schematic diagram illustrating one implementation of athermal analysis tool according to the present invention;

FIG. 3 is a flow diagram illustrating one embodiment of a method forperforming three-dimensional thermal analysis of a semiconductor chipdesign according to the present invention;

FIG. 4 is a graph illustrating the change in value of transistorresistance for an exemplary negative channel metal oxide semiconductoras a function of the output transition voltage;

FIG. 5 is a flow diagram illustrating one embodiment of a method fornormalizing thermal gradients over a semiconductor chip design,according to the present invention;

FIG. 6 is a block diagram illustrating one exemplary embodiment of asemiconductor chip design that may be analyzed in accordance with themethod of FIG. 5;

FIG. 7 is a schematic diagram illustrating one embodiment of asupplemental heat source according to the present invention; and

FIG. 8 is a high level block diagram of the present thermal gradientnormalization tool that is implemented using a general purpose computingdevice.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures.

DETAILED DESCRIPTION

Embodiments of the invention generally provide a method and apparatusfor normalizing thermal gradients over semiconductor chip designs. Oneembodiment of the inventive method produces a full, three-dimensionalsolution of temperature values within a chip design, including powerdissipation values distributed over semiconductor devices (e.g.,transistors, resistors, capacitors, diodes and the like) and wireinterconnects. Chip designers may use this knowledge to guide theplacement of supplemental heat sources for normalizing (e.g., reducingthe large variations in) thermal gradients over chip designs, therebyproducing more robust semiconductor chips.

As used herein, the term “semiconductor chip” refers to any type ofsemiconductor chip, which might employ analog and/or digital designtechniques and which might be fabricated in a variety of fabricationmethodologies including, but not limited to, complementary metal-oxidesemiconductor (CMOS), bipolar complementary metal-oxide semiconductor(BiCMOS), and gallium arsenide (GaAs) methodologies. Furthermore, asused herein, the term “semiconductor device” refers to a potentialactive heat dissipating device in a semiconductor chip, including, butnot limited to, transistors, resistors, capacitors, diodes andinductors. The terms “wire”, “interconnect” or “wire interconnect” asused herein refer to any of various means of distributing electricalsignals (which may be analog or digital, static or dynamic, logicsignals or power/ground signals) from one place to another.“Interconnects” may be on a semiconductor chip itself, used in thepackaging of the semiconductor chip, deployed between the semiconductorchip and the packaging, or used in a variety of other ways.

FIG. 2 is a schematic diagram illustrating one implementation of athermal analysis tool 200 according to the present invention. Asillustrated, the thermal analysis tool 200 is adapted to receive aplurality of inputs 202 a-202 g (hereinafter collectively referred to as“inputs 202”) and process these inputs 202 to produce a full-chip (e.g.,three-dimensional) thermal model 204 of a proposed semiconductor chipdesign.

In one embodiment, the plurality of inputs 202 includes industrystandard design data 202 a-202 f (e.g., pertaining to the actual chipdesign or layout under consideration) and library data 202 g (e.g.,pertaining to the semiconductor devices and interconnects incorporatedin the design). In one embodiment, the industry standard design dataincludes one or more of the following types of data: electricalcomponent extraction data and extracted parasitic data (e.g., embodiedin standard parasitic extraction files, or SPEFs, 202 a), designrepresentations including layout data (e.g., embodied in LibraryExchange Format/Design Exchange Format, or LEF/DEF files 202 b,Graphical Design Format II, or GDSII, files 202 c and/or text files 202d), manufacturer-specific techfiles 202 e describing layer informationand package models, user-generated power tables 202 f including designdata (e.g., including a switching factor, E(sw)). In one embodiment,this industry standard design data 202 a-202 f is stored in a designdatabase such as an open access database or a proprietary database. Inone embodiment, the library data 202 g is embodied in a library that isdistributed by a semiconductor part manufacturer or a library vendor. Inanother embodiment, the library incorporating the library data 202 g canbe built in-house by a user.

In one embodiment, the library data 202 g includes transistor and diodemodels that are used to characterize the transistor resistances (R_(dv))of the driver circuits, e.g., such as models available through Berkeleyshort-channel Insulated Gate Field Effect Transistor (IGFET) model(BSIM) models used by circuit simulators including Simulation Programwith Integrated Circuit Emphasis (SPICE), HSPICE, commercially availablefrom Synopsys, Inc. of Mountain View, Calif. and HeterogeneousSimulation Interoperability Mechanism (HSIM, commercially available fromNassda Corporation of Santa Clara, Calif.), all developed at theUniversity of California at Berkeley.

As mentioned above, the plurality of inputs 202 are provided to thethermal analysis tool 200, which processes the data in order to producea full-chip thermal model 204 of a proposed semiconductor chip design.In one embodiment, the full-chip thermal model is a three-dimensionalthermal model.

Thus, as described above, embodiments of the present invention rely onlibrary data representing the electrical properties of a semiconductorchip design (e.g., the resistance and capacitance at various points) andthe manners in which these properties may vary with respect to eachother and with respect to other phenomena (e.g., temperature orfabrication variations). Those skilled in the art will appreciate thatthese electrical properties may be specified or calculated in any numberof ways, including, but not limited to, table-driven lookups, formulasbased on physical dimensions, and the like.

FIG. 3 is a flow diagram illustrating one embodiment of a method 300 forperforming full-chip thermal analysis of a semiconductor chip designaccording to the present invention. The method 300 may be implemented,for example, in the thermal analysis tool 200 illustrated in FIG. 2. Inone embodiment, the method 300 relies on the computation of powerdissipated by various semiconductor devices of the semiconductor chipdesign. As will be apparent from the following discussion, this powercomputation may be performed in any number of ways, including, but notlimited to, table-driven lookups, computations based on electricalproperties, circuit simulations, and the like. Moreover, those skilledin the art will appreciate that although the following descriptiondiscusses the effects of resistance on power dissipation, powerdissipation computations could be based on any number of otherelectrical properties or parameters, including, but not limited to,capacitance, inductance and the like. Moreover, the computations couldbe static or dynamic.

The method 300 is initialized at step 302 and proceeds to step 304,where the method 300 determines the collection of semiconductor devices(e.g., transistor, resistors, capacitors, diodes inductors and the like)and their resistances. In one embodiment, the method 300 determines thisinformation by reading one or more of the chip layout data (e.g., in GDS11, DEF and/or text format), layer and package model data (e.g., fromone or more techfiles), and initial power and power versus temperaturedata for the semiconductor devices (e.g., from the library data). In oneembodiment, initial power values and power values as a function oftemperature may be recorded within a common power table for acceptableoperating ranges for the driver circuits within the chip design. Thedriver circuits may be at semiconductor device level or at cell level,where cell level circuits represent an abstraction of interconnectedsemiconductor devices making up a known function.

In step 306, the method 300 uses the information collected in step 304to calculate the time average resistance values for every semiconductordevice in every driver circuit of the chip design, as well as for everydiode junction. These time-average resistance values relate to changesin semiconductor device dimensions (e.g., such as using higher powertransistors in place of lower power transistors in a chip design). Inone embodiment, the time average resistance value, R_(average) for asemiconductor device is calculated as:

$\begin{matrix}{R_{average} = \frac{\int_{0}^{t_{r}}{R\ {{v(t)}}{t}}}{t_{r}}} & \left( {{EQN}.\mspace{14mu} 1} \right)\end{matrix}$

where t_(r) is the output transition time of the driver circuit underconsideration, e.g., as specified by the library data.

FIG. 4 is a graph illustrating the change in value of transistorresistance, R_(dv) for an exemplary negative channel metal oxidesemiconductor (nMOS) as a function of the output transition voltage,V_(driver) _(out) . As illustrated, the power dissipated by a transistorvaries during switching. This is also true for the power dissipated inother semiconductor devices and in the interconnects coupled to thesemiconductor devices on the chip.

Referring back to FIG. 3, in step 308, the method 300 calculates thepower dissipated by the semiconductor devices and interconnects at agiven temperature for the design under consideration. In one embodimentof step 308, e.g., where a steady-state analysis of the chip design isbeing performed, the interdependence of temperature and average power iscaptured through pre-characterized parameters of the semiconductordevices and interconnects. In one embodiment, the power dissipated by asemiconductor device (in this exemplary case, a transistor),P_(transistor), is calculated as:

P _(transistor)=(V _(d))² /R _(average)  (EQN. 2)

where V_(d) is the power supply voltage supplied to the transistor. Thisvoltage, V_(d), is less than the actual power supply voltage, V_(dd), asthe current drawn by the transistors and flowing through theinterconnects that connect the transistors to a power supply causes avoltage drop. In another embodiment, the power supply voltage to thetransistor V_(d) could be divided by the maximum or minimum resistancevalue, R_(max) or R_(min), in order to calculate the power dissipated inthe transistor. In one embodiment, a decision as to whether to use anaverage, minimum or maximum resistance value to calculate P_(transistor)is based at least in part on whether additional conditions, such as theoperation of the circuit, are to be evaluated.

While equations for calculating the power dissipation of transistorshave been provided herein by way of example, those skilled in the artwill appreciate that various methods of calculating power dissipationfor other semiconductor devices, such as resistors, capacitors anddiodes, are known in the art. For example, equations for calculating thepower dissipation of a resistor are discussed in the Proceedings of theFourth International Symposium on Quality Electronic Design (ISQED2003), 24-26 Mar. 2003, San Jose, Calif.

In one embodiment, the power dissipated by the interconnects (e.g.,power and signal lines), P_(interconnect) is calculated as:

P _(interconnect) =P−P _(transistor)  (EQN. 3)

where P is the average electrical power dissipated per clock cycle by adigital circuit (e.g., the chip design under consideration; for the fullchip, the total P is the sum of the power dissipated by each circuit inthe chip) and is available from the library data 202 g. In the powerlines, power is typically dissipated as Joule heating, where thedissipated power P_(dissipated) may be calculated as:

P_(dissipated)=I_(p) ²R_(power)  (EQN. 4)

where I_(p) is the current through the power lines and R_(power) is theresistance of the power bus. The value of Ip may be calculated bycommercially available tools, such as Voltage Storm, available fromCadence Design Systems, Inc. of San Jose, Calif.

Typically, the power drawn by a switching transistor may be calculatedas:

P=C _(load) V _(dd) E(sw)(fclk)  (EQN. 5)

where C_(load) is the output capacitance as seen by the circuit, E(sw)is the switching activity as defined by the average number of outputtransitions per clock period, and fclk is the clock frequency. Theswitching factor or acrivity, E(sw), is used for evaluating the powertable for the initial state of the design. C_(load) may be calculated byparasitic extraction tools, and values for fclk and V_(dd) are typicallyspecified for a given design. In general, half of the power, P, isstored in the capacitance and the other half is dissipated in thetransistors and interconnects (e.g., the power and signal lines). Thoseskilled in the art will appreciate that since R_(average) varies withthe transition time of the circuits, and as the switching activitychanges for different modes of operation, E(sw) will also change,thereby changing the value of P and the distribution of the amounts ofpower dissipated in the transistors (e.g., see Equation 2) andinterconnects. This will, in turn, change the heat fields andcorresponding temperatures within the chip.

In another embodiment of step 308, a transient analysis is performed,wherein the interdependence of temperature and average power in thesemiconductor devices and interconnects is based on instantaneous valuesof power. In this case, power dissipated values are calculated bydynamically simulating the circuit embodied in the chip design underconsideration. For example, the circuit may be simulated using anycommercially available circuit simulator, such as HSPICE or HSIM,discussed above, or SPECTRE, commercially available from Cadence DesignSystems. In one embodiment, the circuit is simulated by solving forvalues of electrical attributes (e.g., current and voltages) at variouspoints in time. In the case of transient thermal analysis, the thermalanalysis system (e.g., thermal analysis tool 200 of FIG. 2) drives thecircuit simulator to calculate power at discrete points whenever thereis a sufficient change in the temperature of the circuit. In oneembodiment, the sufficiency of a temperature change for these purposesis determined by a predefined threshold.

In step 310, the method 300 distributes the power consumed in each ofthe interconnects. In one embodiment, power is distributed based on theresistance of the wires used in the interconnects, which is defined bythe type, thickness and height of the wires used in the interconnects.In one embodiment, the resistance, R_(interconnect), of an interconnectsegment is calculated as:

$\begin{matrix}{R_{interconnect} = \frac{\rho \; L}{wt}} & \left( {{EQN}.\mspace{14mu} 6} \right)\end{matrix}$

where L is the length of the interconnect segment, w is the width of thesegment, t is the thickness of the segment, and ρ is a resistivityconstant dependent upon the type of wire used. The resistivity constant,ρ, may be found in tables included in any number of integrated circuitstextbooks, including Rabaey et al., Digital Integrated Circuits, SecondEdition, Prentice Hall Electronic and VLSI Series, 2002.

In step 312, the method 300 uses the power dissipation and distributioninformation calculated in steps 306-310 to model a full-chip (e.g.,three-dimensional) temperature gradient over the chip design underconsideration. In one embodiment, a full-chip temperature gradient ismodeled by adaptively partitioning the volumes of steep temperaturegradients over the chip design. In one embodiment, partitioning is donein three dimensions; however, in other embodiments, partitioning may bedone in one or two dimensions as well (for example, verticalpartitioning may be explicitly considered in how the temperature ismodeled). In one embodiment, “steep” temperature gradients are thoseportions of the overall temperature gradient that are steep relative toother regions of the overall temperature gradient. In one embodiment,techfile data (e.g., pertaining to the dimensions and properties of thechip design layers) and power density data are used to partition thechip design. Power density data is typically contained within the powertable provided for a particular state of operation of a chip design. Thetemperatures in each partition are then determined and annotatedaccordingly in the three-dimensional model.

In step 314, the method 300 determines whether the currently computedtemperature for the chip design falls within a previously specifiedrange. If the method 300 concludes that the currently computedtemperature does not fall within this range, the method 300 proceeds tostep 318 and modifies the chip design (e.g., by changing the resistancesof the semiconductor devices and interconnects, resizing thesemiconductor devices and interconnect wires, etc.). The method 300 thenreturns to step 308 and proceeds as discussed above.

Alternatively, if the method 300 determines that the currently computedtemperature does fall within the specified range, the method 300proceeds to step 316 and terminates. Thus, steps of the method 300 maybe repeated in an iterative manner until a steady state value isreached, within a specified tolerance. In one embodiment, iteration ofthese steps may depend on the particular implementation of the method300. In further embodiments, iteration could include convergence to anabsolute value, convergence to a relative value, or the passing of afixed number or iterations or a fixed amount of time.

Thus, the method 300 employs industry standard design, package and heatsink data in order to produce a more complete and more accurate profileof the temperature gradient created by a semiconductor chip design. Byaccounting for the distribution of power dissipated in the semiconductordevices and in the interconnects, rather than simply characterizingdissipated power as the power dissipated in the active semiconductordevices (which does not consider simultaneous changes in theelectrothermal properties of the semiconductor devices andinterconnects), more accurate, full-chip thermal profiling can beachieved.

Chip designers may use the full-chip data produced by the method 300 todesign more robust semiconductor chips for particular applications. Forexample, if the full-chip temperature gradient produced by one iterationof the method 300 does not illustrate acceptable results for asemiconductor chip design, a chip designer may go back and modify thechip design (e.g., by changing the resistances of the semiconductordevices and interconnects, resizing the semiconductor devices andinterconnect wires, etc.) in an attempt to achieve more desirableresults. The method 300 may then be applied to the modified design toassess the resultant temperature gradient. Those skilled in the art willappreciate that while the method 300 illustrates a series of steps, thepresent invention is not limited to the particular sequence illustrated,and thus FIG. 3 should be considered only as one exemplary embodiment ofthe present invention.

In one embodiment, knowledge of full-chip temperature gradients may beused to normalize (e.g., reduce large variations in) the gradients oversemiconductor chip designs. For example, a chip designer can normalizethe thermal gradient over a semiconductor chip by identifying andaddressing those regions of the chip where the thermal variations aremost pronounced.

FIG. 5 is a flow diagram illustrating one embodiment of a method 500 fornormalizing thermal gradients over a semiconductor chip design,according to the present invention. The method 500 is initiated at step502 and proceeds to step 504, where the method 500 receives full-chiptemperature data for a semiconductor chip design. The full-chiptemperature data may be calculated, for example, in accordance with themethod 300 described above.

In step 506, the method 500 analyzes, based on the full-chip temperaturedata, the thermal gradients over or between each pair of semiconductordevices in the semiconductor chip design. That is, each thermal gradientthat exists between two semiconductor devices is calculated.

For example, FIG. 6 is a block diagram illustrating one exemplaryembodiment of a semiconductor chip design 600 that may be analyzed inaccordance with the method 500. The semiconductor chip design 600comprises a substrate 602 upon which a plurality of heat-generatingsemiconductor devices 604 ₁-604 _(n) (hereinafter collectively referredto as “semiconductor devices 604”) are positioned. In accordance withthe step 506 of the method 500, thermal gradients between, for example,semiconductor devices 604 ₁ and 604 ₂, semiconductor devices 604 ₁ and604 ₄ and semiconductor devices 604 ₁ and 604 ₅, among others, would beanalyzed.

Referring back to FIG. 5, in step 508, the method 500 determines whetherall of the thermal gradients over all of the semiconductor device pairsare within predefined limits for the semiconductor chip design (e.g., asdictated by design constraints). If the method 500 determines in step508 that all of the thermal gradients are within the predefined limits,the method 500 terminates in step 522.

Alternatively, if the method 500 determines in step 508 that all of thethermal gradients are not within the predefined limits (e.g., one ormore thermal gradients exceeds the predefined limits), the method 500proceeds to step 510 and sorts the pairs of semiconductor devices whosethermal gradients exceed the predefined limits. In one embodiment, thesemiconductor device pairs are sorted according to the magnitudes of theassociated thermal gradients (e.g., smallest thermal gradient tolargest) and entered in a queue. In FIG. 6, the dashed line 608illustrates a temperature gradient across semiconductor devices 604 ₅and 604 ₆ that exceeds predefined limits for the semiconductor chipdesign 600; thus, the thermal gradient between semiconductor devices 604₅ and 604 ₆ would be sorted in accordance with step 510.

In step 512, the method 500 identifies, for each thermal gradient sortedin step 510, one or more locations in the semiconductor chip design inwhich a supplemental heat source may be placed. In one embodiment, asupplemental heat source is a controlled power source (e.g., a set ofmetal-oxide semiconductor (MOS) transistors or a resistance having acontrolled current through it) that is configured to dissipate a knownamount of heat. In one embodiment, locations for supplemental heatsources are selected to mirror the positions of the semiconductordevices across which the overly large thermal gradients occur (e.g.,such that the arrangement of semiconductor devices and supplemental heatsources is symmetric about an axis). Thus, for example, in FIG. 6, alocation for a first supplemental heat source 606 ₁ is selected toreflect semiconductor device 604 ₆ about axis A-A′, and a location for asecond supplemental heat source 606 _(n) is selected to reflectsemiconductor device 604 ₅ about axis A-A′.

Placement of supplemental heat sources will depend in part on theavailability of space in the neighborhood of the semiconductor devices.To compensate for this restriction on location, the power values of thesupplemental heat sources may be adjusted based on thermal gradientvalues, as discussed in further detail below. In one embodiment, twosupplemental heat sources are implemented to normalize the thermalgradient: one “upstream” supplemental heat source and one “downstream”supplemental heat source on either side of the pair of semiconductordevices whose thermal gradient requires normalization.

In step 514, the method 500 places or inserts one or more supplementalheat sources into the semiconductor chip design, in one or more of thelocations identified in step 512.

In step 516, the method 500 assigns a power value to each supplementalheat source that has been inserted into the semiconductor chip design.In one embodiment, the power value initially assigned to a supplementalheat source is substantially equal to the power value of thesemiconductor device that the supplemental heat source is positioned toreflect. Thus, for example, in FIG. 6, the initial power value set instep 516 for the supplemental heat source 606 ₁ would be substantiallyequal to the power value of the semiconductor device 604 ₆.

Once power values have been assigned to all supplemental heat sources,the method 500 proceeds to step 518 and recomputes the thermalgradients. In one embodiment, the thermal gradients are recomputed byrecomputing the full-chip temperature data, e.g., in accordance with themethod 300 described above.

In step 520, the method 500 determines whether, in light of theinsertion of the supplemental heat sources, all of the thermal gradientsover all of the semiconductor device pairs are now within the predefinedlimits. If the method 500 determines in step 520 that all of the thermalgradients are now within the predefined limits, the method 500terminates in step 522.

Alternatively, if the method 500 determines in step 520 that all of thethermal gradients are not within the predefined limits, the method 500returns to step 516, and, for each thermal gradient that exceeds thepredefined limits, re-assigns or adjusts the power values for theassociated supplemental heat sources that have been inserted. In oneembodiment, the power values for the associated supplemental heatsources are increased by the amount TkS, where T is the difference intemperature between the semiconductor devices across which the thermalgradient occurs, k is the thermal conductivity of the materialseparating the supplemental heat source from the cooler of thesemiconductor devices across which the thermal gradient occurs and S isthe shape factor of the material separating the supplemental heat sourcefrom the cooler of the semiconductor devices across which the thermalgradient occurs. As described athttp://granular.che.pitt.edu/˜mccarthy/che1011/Cond/Multi/shape_factors.html,the shape factor of a material is geometry-dependent.

The method 500 then proceeds from step 516 as described above, repeatingas many iterations of steps 516-520 as is necessary to bring all thermalgradients in the semiconductor chip design within the predefined limits.

In this manner, the method 500 normalizes thermal gradients that exceeddesign limitations by inserting supplemental heat sources in strategiclocations within the semiconductor chip design. The supplemental heatsources are configured to dissipate heat such that variations in thethermal gradient are reduced, thereby bringing the semiconductor chipdesign within the design constraints imposed thereon.

In one embodiment, supplemental heat sources are inserted to account forworst-case thermal gradient conditions, e.g., using full-chip thermalanalysis of the semiconductor chip design. In another embodiment, powervalues of the inserted supplemental heat sources can be adjusted in realtime in response to a measured state of heat dissipation within asemiconductor chip design (e.g., monitored using control circuits andtemperature measurement devices). In yet another embodiment, knownstates of the supplemental heat sources are simulated in a full-chipthermal analysis, and, for specific states of the supplemental heatsources, control input is set to dissipate required amounts of heat(e.g., to normalize observed thermal gradients).

FIG. 7 is a schematic diagram illustrating one embodiment of asupplemental heat source 700 according to the present invention. In oneembodiment, the supplemental heat source 700 comprises one or more heatdissipating devices 702 ₁-702 _(n) (hereinafter collectively referred toas “heat dissipating devices 702”) coupled to a control device 704 andto a power rail 706. In addition, the control device 704 is coupled to aground rail 708.

The control device 704 is configured to control, in response to acontrol signal or input, the power provided to the heat dissipatingdevices 702.

In one embodiment, the heat dissipating devices 702 are MOS transistorsvirtually disconnected from power. In this embodiment, the controldevice 704 is a transistor whose control gate is connected to anycircuit that can be activated by connecting to a fixed voltage. In thecase where the supplemental heat source 700 is inserted to account for aparticular worst-case thermal gradient condition, the control device 704is a fixed voltage control source.

In another embodiment, the control device 704 is connected to controllogic that monitors the thermal gradients of a semiconductor chip designin real time. In this case, the control device 704 uses a programmablecontrolled logic circuit to scale the heat dissipated by the heatdissipating devices 702. The magnitude of heat dissipated by the heatdissipating devices may be determined by prior full-chip thermalanalysis (e.g., in accordance with the method 300).

FIG. 8 is a high level block diagram of the present thermal gradientnormalization tool that is implemented using a general purpose computingdevice 800. In one embodiment, a general purpose computing device 800comprises a processor 802, a memory 804, a gradient normalization module805 and various input/output (I/O) devices 806 such as a display, akeyboard, a mouse, a modem, a network connection and the like. In oneembodiment, at least one I/O device is a storage device (e.g., a diskdrive, an optical disk drive, a floppy disk drive). It should beunderstood that the gradient normalization module 805 can be implementedas a physical device or subsystem that is coupled to a processor througha communication channel.

Alternatively, the gradient normalization module 805 can be representedby one or more software applications (or even a combination of softwareand hardware, e.g., using Application Specific Integrated Circuits(ASIC)), where the software is loaded from a storage medium (e.g., I/Odevices 806) and operated by the processor 802 in the memory 804 of thegeneral purpose computing device 800. Additionally, the software may runin a distributed or partitioned fashion on two or more computing devicessimilar to the general purpose computing device 800. Thus, in oneembodiment, the gradient normalization module 805 for normalizingthermal gradients over semiconductor chip designs described herein withreference to the preceding figures can be stored on a computer readablemedium or carrier (e.g., RAM, magnetic or optical drive or diskette, andthe like).

Thus, the present invention represents a significant advancement in thefield of semiconductor chip design. One embodiment of the inventionprovides an inventive method for normalizing thermal gradients oversemiconductor chip designs. In particular, the inventive method producesa full, three-dimensional solution of temperature values within a chipdesign, including power dissipation values distributed oversemiconductor devices (e.g., transistors, resistors, capacitors, diodesand the like) and wire interconnects. Chip designers may use thisknowledge to guide the placement of supplemental heat sources fornormalizing (e.g., reducing the large variations in) thermal gradientsover chip designs, thereby producing more robust semiconductor chips.

While the foregoing is directed to embodiments of the invention, otherand further embodiments of the invention may be devised withoutdeparting from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

1. A method for normalizing a thermal gradient in a semiconductor chipdesign, the method comprising: determining a location of said thermalgradient; and inserting at least one supplemental heat source into saidsemiconductor chip design such that said thermal gradient is normalizedby heat dissipated by said at least one supplemental heat source.
 2. Themethod of claim 1, wherein said determining is performed in accordancewith full-chip temperature data for said semiconductor chip design. 3.The method of claim 1, wherein said inserting comprises: selecting alocation for said at least one supplemental heat source; and assigning apower value to said at least one supplemental heat source.
 4. The methodof claim 3, wherein said thermal gradient occurs between a firstsemiconductor device and a second semiconductor device that is coolerthan said first semiconductor device.
 5. The method of claim 4, whereinsaid selecting comprises: positioning said at least one supplementalheat source to mirror a position of at least one of said firstsemiconductor device and said second semiconductor device.
 6. The methodof claim 3, further comprising: computing full-chip temperature data forsaid semiconductor chip design, including said at least one supplementalheat source; and adjusting said power value if said thermal gradientexceeds a design constraint applicable to said semiconductor chipdesign.
 7. The method of claim 6, wherein said adjusting comprises:increasing said power value by an amount substantially equal to adifference in temperature between said first semiconductor device andsaid second semiconductor device multiplied by a thermal conductivity ofa material separating said at least one supplemental heat source fromsaid second semiconductor device multiplied by a shape factor of saidmaterial.
 8. The method of claim 3, wherein said assigning comprises:assigning said power value to account for a worst-case condition forsaid thermal gradient.
 9. The method of claim 3, wherein said assigningcomprises: adjusting said power value in real time in response to ameasured state of heat dissipation within said semiconductor chipdesign.
 10. The method of claim 1, wherein said at least onesupplemental heat source is a controlled power source that is configuredto dissipate a known amount of heat.
 11. A computer readable mediumcontaining an executable program for normalizing a thermal gradient in asemiconductor chip design, where the program performs the steps ofdetermining a location of said thermal gradient; and inserting at leastone supplemental heat source into said semiconductor chip design suchthat said thermal gradient is normalized by heat dissipated by said atleast one supplemental heat source.
 12. The computer readable medium ofclaim 11, wherein said determining is performed in accordance withfull-chip temperature data for said semiconductor chip design.
 13. Thecomputer readable medium of claim 11, wherein said inserting comprises:selecting a location for said at least one supplemental heat source; andassigning a power value to said at least one supplemental heat source.14. The computer readable medium of claim 13, wherein said thermalgradient occurs between a first semiconductor device and a secondsemiconductor device that is cooler than said first semiconductordevice.
 15. The computer readable medium of claim 14, wherein saidselecting comprises: positioning said at least one supplemental heatsource to mirror a position of at least one of said first semiconductordevice and said second semiconductor device.
 16. The computer readablemedium of claim 13, further comprising: computing full-chip temperaturedata for said semiconductor chip design, including said at least onesupplemental heat source; and adjusting said power value if said thermalgradient exceeds a design constraint applicable to said semiconductorchip design.
 17. The computer readable medium of claim 16, wherein saidadjusting comprises: increasing said power value by an amountsubstantially equal to a difference in temperature between said firstsemiconductor device and said second semiconductor device multiplied bya thermal conductivity of a material separating said at least onesupplemental heat source from said second semiconductor devicemultiplied by a shape factor of said material.
 18. The computer readablemedium of claim 13, wherein said assigning comprises: assigning saidpower value to account for a worst-case condition for said thermalgradient.
 19. The computer readable medium of claim 13, wherein saidassigning comprises: adjusting said power value in real time in responseto a measured state of heat dissipation within said semiconductor chipdesign.
 20. The computer readable medium of claim 11, wherein said atleast one supplemental heat source is a controlled power source that isconfigured to dissipate a known amount of heat.
 21. Apparatus fornormalizing a thermal gradient in a semiconductor chip design, theapparatus comprising: means for determining a location of said thermalgradient; and means for inserting at least one supplemental heat sourceinto said semiconductor chip design such that said thermal gradient isnormalized by heat dissipated by said at least one supplemental heatsource.